The present invention relates generally to impedance matching techniques for integrated circuits and, more particularly, to a method and apparatus for impedance matching in transmission circuits using tantalum nitride based resistor devices.
It is well known that for high speed transmission circuits, the matching of input impedance, drive impedance, pull-up/pull-down resistance, and the like between circuits and components is an essential aspect of suppressing reflection of a transmitted signal so as to allow transmission of high quality high speed signals. However, the realities of the manufacturing processes of circuit components such as resistors, capacitors, and transistors are such that the resulting electrical parameters such as resistance and capacitance values can vary (for example) by about ±20% or more.
Accordingly, impedance trimming and matching networks are commonly used in conjunction with high speed transmission components in order to more precisely match, for example, input (transmission) circuit impedance to transmission line impedance. FIG. 1 is a schematic diagram of a conventional impedance matching circuit 100 utilizing switching “finger” resistors. As is shown, the circuit 100 includes three identical finger resistor networks: reference resistor network 102 and transmission resistor networks 104A, 104B. Resistor R0 is an external precision resistor representing the impedance to be matched by the transmission resistor networks associated with the transmission line.
Circuit 100 also includes a comparator 106, pulse generator 108, and an increment/decrement counter 110 forming a closed loop within a reference path in order to determine a specific combination of the finger resistors that are tuned “on” (i.e., connected) to the transmission line in order to match R0. In particular, resistor networks 102, 104A and 104B each include a plurality of individual resistors Rn1, Rn2, . . . , Rnn selectively coupled to a voltage supply bus (Vcc) through a series of corresponding PFET devices pn1, pn2, . . . , pnn. Control signals for each of the PFET devices are generated from the operation of the pulse generator 108 and increment/decrement counter 110.
In order to determine which combination of the finger resistor networks is activated (coupled to Vcc) so as to match R0, identical current sources I0, I1 are used to generate voltages at nodes Va, Vb, respectively. Thus, if the effective resistance of reference network 102 equals that of R0, the voltage at Va equals the voltage at Vb and no signal is output from comparator 106. In turn, pulse generator 108 and increment/decrement counter 110 do not change the state of any of the PFET devices in the finger networks 102, 104A, 104B. On the other hand, if the effective resistance of reference network 102 no longer equals that of R0, the voltage at Va will no longer equals the voltage at Vb and a, signal is output from comparator 106 (the polarity of which will depend on whether Va is greater or less than Vb. In turn, pulse generator 108 and increment/decrement counter 110 will operate to change the state of one or more of the PFET devices in the finger networks 102, 104A, 104B, thus dynamically adjusting the resistance thereof such that they are equal to R0.
Unfortunately, the finger resistor network scheme of circuit 100 has various disadvantages associated therewith. For instance, it is assumed that the resistance in each finger of reference network 102 is identical to that of networks 104A and 104B. However, in real devices, process variations can result in mismatches between the “identical” resistors/PFETs of the networks. Thus, even if the closed loop system of circuit 100 can match R0 to the resistance of reference 102, this is not a guarantee that the identical control configuration applied to the finger resistors of networks 104A and 104B will also be identical to R0.
Furthermore, the on-line switching of the resistor fingers generates voltage glitches on the (NFETs) N1A, N1B outputs, which can cause signal jitter in the transmission line. Another shortcoming of the circuit 100 is that the parasitic capacitance is large. Although, the “turned off” fingers provide no contribution to the total resistance of networks 104A and 104B, the parasitic capacitance of all the fingers is continuously coupled to the output nodes of N1A and N1B. Moreover, conventionally formed resistors, such as BR and OP (define) resistors, are physically located close to the device substrate, thus their parasitic capacitance is relatively large. As is well known, parasitic capacitance affects impedance matching, especially for high-speed applications.